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NeuRAM3 results in the press

EE News logo Experimenting with neural architectures in silicon

EE Times logo AI’s Limits Send Scientists Back to the Brain


 

NeuRAM3 FDSOI 28nm Neuromorphic Processing Unit (NPU)

Multi-core spiking neural network chip with mixed signal analog/digital neurons and synapses, and in-memory computing asynchronous architecture. Ultra-low power and low-latency performance, with multiple distributed memory structures ideal for co-integration with resistive memory technologies.

FDSOI neuromorphic processing unit



The ReASOn chip

NeuRAM3 130 CMOS Neuromorphic Processing Unit with co-integration or ReRAM and CMOS synapse circuits.


NeuRAM3 NPU test setup

Setup framework for exploring on-line spiking neural network architectures

Neuram3 test setup


Layout of the IMSE ReRAM test circuits.

IMSE circuits layout


Operative Connection of RRAM Synapse to VLSI Neurons

The asynchronous plasticity operation of a block constituted by one RRAM synapse and two VLSI mixed-signal digital-analogue subthreshold neurons is demonstrated by a collaboration between CNR and UZH. The RRAM synapse is produced by CNR and can be operated in analogue and in digital manners. The neuron chip is designed by UZH and comprises neuron/synapse interfaces that allow the managing of the voltage drop on the synapse terminals in such a way that long term potentiation or depression events are triggered in an asynchronous manner and according to a generalized version of a Spike Timing Dependent Plasticity. The work (published here) constitutes a first step towards a realistic implementation VLSI-compatible asynchronous neuromorphic systems comprising RRAM synapses.

RRAM synapseCNR_3_2

 

Photograph and schematic of the experimental setup. Schematic insets: micro-photograph of the memristive devices (round inset, top left) and micro-graph of the neuromorphic die (square inset, bottom right).


 

Analog Non-Linear Soft-Bound Switching Dynamics Filamentary RRAMs

Our participants from the CNR demonstrate that under suitable programming conditions filamentary HfO2-based devices undergo an analog switching dynamics with non-linear conductance evolution as a function of the number of identical delivered pulses, as shown in the figure below (reprinted according to CC-BY 4.0 license from the publication reported below). The dynamics evolve with a soft approach to the conductance boundary values, according to the soft-bound model as formulated by Fusi and Abbott (Nature Neuroscience (2007) 10 485), who demonstrate that such dynamics improve the memory capacity and the lifetime of the memories stored in a corresponding synaptic matrix.

In addition, the quantitative estimation of the soft-bound model parameters allows to obtain a relative evaluation of the resolution of an electronic synapse, to identify the programming margin for analog operation and the existing trade-offs between resolution, resistance window (Rmax/Rmin), linearity and symmetry between the processes of conductance increase and decrease.

CNR_1

Sequences of 300 identical pulses for different programming conditions. In black lines, fit to data of the generalized soft bound model. (a) Potentiation operations for a fixed ΔV of −0.7 V at different Δt; (b) Depression operations operated at ΔV = +0.9 V and different Δt; (c) Potentiation curves obtained at Δt = 10 μs and different ΔV; (d) Depression curves for Δt = 100 μs and different ΔV. From https://www.nature.com/articles/s41598-018-25376-x



Development of Models for RRAM Devices

CNR developed physics inspired models to describe the electrical behaviour of HfO2-based RRAMs. A deterministic filamentary model and a stochastic model have been elaborated as described in the following.

Deterministic Filamentary Model – The effect of Al doping of the switching HfO2 oxide of RRAM device has been modelled according to a filamentary model the developed model, the ON (low resistance) and the OFF (high resistance) states of a metal/insulator/metal device are described in terms of a continuous and an interrupted filament in between the two electrodes. The drift and diffusion of defects constituting the CF are provoked by electric field and self-heating due to current flowing.

The model is described here, where it is used to understand the different switching features of Pt/HfO2/TiN devices with and without Al doping of the Hf oxide, as reported in the figure below.

CNR_2_1
Experimental (symbols) and modelled (lines) RESET curves of Pt/HfO2/TiN (a) and Pt/Al:HfO2/TiN (b) devices. Panels (c) and (d) report the filament configurations (left axis) for gap lengths equal to 0.08, 2.4 nm for both HfO2 and Al:HfO2 devices at points A and B, respectively. In the same panels, (right axis) the temperature profiles along the filament axis are shown as (blue) straight and (red) dashed lines for HfO2 and Al:HfO2 devices, respectively.

Stochastic Model – CNR developed a stochastic model based on a network of circuit breakers playing the role of the switching medium of a RRAM, as sketched in the figure below. Each breaker switches according to a probability that depends on its temperature and the voltage drop over it. The model catches the salient features of the RRAM switching. As described in: S. Brivio, S. Spiga, "Stochastic circuit breaker network model for bipolar resistance switching memories", Journal of Computational Electronics, 16 1154 (2017). http://link.springer.com/10.1007/s10825-017-1055-y

CNR_2_2
Sketches of the breaker network (a) and of the device metal/insulator/metal stack (b). 



1-bit Weights Stochastic STDP on the Poker-DVS dataset

When using the Poker-DVS dataset, a 1-bit weights STDP layer (followed by a multi-bit event-driven classifier layer) allows for same recognition than 8-bit STDP but with less hardware resources, while at the same time producing less spikes:

 Poker DVS layout


 

Ultra-low power switching fabric for scaling towards large multi-core spiking neural network architectures

Large scale neuromorphic systems are aiming for the ‘human brain size’ complexity that is needed for massive search and analysis tasks while interacting with physical signals. Such a system would consist of similar number of neurons and synapses as in an adult human brain. One of the main challenges is the massive synaptic complexity resulting from connecting billions of neurons.

We present a feasible architecture that could handle the enormous communication bandwidth necessary for such a large-scale neuromorphic system. Inspired by the recent advancements in SoC architecture, a novel scalable inter-cluster communication network is proposed here. A particularly useful instantiation of this occurs for the global synaptic communication, interconnecting the local clusters of synapse arrays. Figure 1. Illustrates the proposed segmented bus architecture interconnecting neural clusters.

IMEC_NL_1

The parallel segmented bus interconnecting neural clusters

The core of the proposed solution is a novel switching architecture in the CMOS back-end-of-line (BEOL) that is expected to be extremely power efficient. Figure 2 depicts a cross section of a typical CMOS wafer with 8 metal BEOL connecting FEOL devices. The BEOL devices acting as a switch (shown in red) can considerably reduce vertical wiring.

IMEC_NL_2

In contrast to a fixed pre-defined bus that is shared over all connected local clusters, the proposed solution will allow a multitude of dedicated point-to-point connections that can be switched dynamically.


 

Mixed-signal neuromorphic platform and real-time ECG classification application demonstrator

IMEC-NL has developed a mixed-signal neuromorphic platform and application demonstrator. Figure 3 shows the hardware platform comprising the analogue Spiking Neural Network (SNN) chips from the UZH and the TFT-based segmented bus (global synapse) chip from IMEC-BE & IMEC-NL.

IMEC_NL_3

IMEC-NL Mixed-signal Neuromorphic Platform Comprising analogue Spiking Neural Network (SNN) chips from the UZH and the TFT-based Segmented Bus (Global Synapse) chip from IMEC-BE & IMEC-NL

The platform uses Zynq FPGA made-up of ARM processor and programmable logic. The spike traffic on the global synapses are encoded as AER packets by the Dynapse chips. These AER packets are routed on the TFT segmented bus as serial AER packets. The programmable logic on Zynq implements serial AER packet encoding/decoding and multiplexing/de-multiplexing functionality.

IMEC-NL has also developed real-time ECG classification and arrhythmia detection algorithm and demonstrator on the hardware neuromorphic platform. The algorithm implements a Liquid-State-Machine (LSM) on the Dynapse neural processors and a Support Vector Machine (SVM) based classifier running as software module on the ARM processor. Figure 4. illustrates the real-time ECG classification and arrhythmia detection implemented using the SNNs and SVM.

The ECG data is encoded as positive and negative change into two channel data and fed to the Liquid State machine (LSM) implemented on hardware SNN. The LSM neuron firing is read and classified using a Support Vector Machine (SVM) implemented in software. The algorithm successfully classifies the normal and arrhythmia heartbeats with over ~86% accuracy.

IMEC_NL_4

Real-time ECG classification and arrhythmia detection