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ReASOn

130 nm CMOS test-chip with integrated memristors.

Introduction

ReASOn (Resistive Array of Synapses with ONline learning) is a test-chip featuring 2048 memristive devices that implement 1024 memory cells connected to 2 neurons via a programmable routing fabric.  The neurons include circuits that implement online learning.This chip is intended for testing a a wide range of memristive devices and monitorthem individually. This chip also features test circuits relevant for neuromorphicapplications including an alpha synpase, shunting synapse, hebbian/anti-hebbian/stoplearning, and a new neuron circuit. All the circuits are highly tunable using external biases to make testing and experimentation easier.

Property
Process 130 nm CMOS with an extra post-processing step
Power domains 1.2 V and 4.7 V
Number of IOs and packaging 104, CQFP128
Area of the chip 2705.16 um x 1905.16 um
Neuron type Leaky Integrate and Fire with learning block
Number of Synapses and Neurons 1024 plastic synapses and 2 neurons

Features

  • Fully-integrated with CMOS by two-stage process
    • Traditional CMOS process to the penultimate metal layer
    • Memristive devices laid on top in a different fab with proper alignment.
  • Can be used to test a variety of memristive devices.

  • Neuromorphic ideas implemented:

    • Learning block for generation of synaptic update pulses and delta current
    • Current comparator neuron design
    • Alpha-function generation block
    • Shunting inhibition
    • Hebbian and anti-Hebbian learning mode
    • Continuous learning

top_level_block_diagram 

The neuromorphic architecture:

The following figure shows the architecture of the neuromorphic components of the test-chip.

Memristive synapses

Challenges with integrating ReRAMs in neuromorphic circuits:

  • Sensing device state as currents
  • Variability and mismatch during programming
  • Device currents too large for post-synaptic neurons
  • Training mechanisms

 

Solution #1: Linearly sensing device state

Diode current mirror technique to almost linearly read device conductance as current:

   

 

Solution #2 - Differential operation to reduce effect of device variability and mismatch

Memory can be stored as difference of conductances of two devices.

  • Reduces effect of mismatch and variability.
  • Differential output implements positive and negative weights.
  • No need to set a decision threshold

    

When the differential cell is used as binary memory cell, the prediction accuracy is improved quite significantly as shown in the following plots that compare the single device case (middle) against that of differential operation (right). Also note the improved symmetry. Different colored traces are the different magnitudes of standard deviations of the sampling distribution of the devices.

Solution #3 - Normalization to reduce currents sunk into downstream neurons

Post-synaptic neurons should operate with currents in the order of nA to:

  • Minimize power consumption.
  • Minimize modeling inaccuracy.
  • Retain biological plausibility.

Ex: 1 V across a 1 MW -> 1 mA current. Too large, especially when integrating large number to synaptic currents.

 

  • Based on the Gilbert-normalizer cell.
  • Differential output - Ipos and Ineg.
  • Works for binary and multi-state devices.
  • When Vsel = 1, read operation is active. 
  • Vb sets the normalized output current.

Simulation highlighting the normalization behaviour of the circuit

Solution #4 - Mismatch in output currents also reduced by normalization

Mismatch the output currents is much smaller than that in the devices themselves because of the normalization behavior.


The complete memristive synapse circuit:

The differential memristive synapse cell including all control switches. Note that the control signals controlling the two branches of the circuit are complementary.

   

In the simulation plot (right):

  • The conductance of device Dpos is swept while keeping Dneg fixed .
  • Simulation of output currents vs device conductance.


Integration of the memristive synapse in the neuromorphic system

Each row of synapses and its associated neuron in the ReASOn test-chip is structured as shown below: 

  • Positive and negative output summed and integrated by separate DPI circuits.
  • Learning block generates update control signals for the synapses.

Features of the neuromorphic system:

  • 1024 synapses or memory cells (comprising 2048 ReRAM elements).
    • Two devices per synapse integrated in a differential mode.
  • Two modes of operation:
    • Neuromorphic mode - Output currents driven to a spiking neuron. 
      • Sensing circuit generates a differential current output that is a function of device conductances.
      • Can monitor synaptic currents at various stages of signal processing. Values are read out using an internal ADC.
      • Memristor array can be trained as a perceptron.
      • Forming and write operations only supported in this mode.
      • Tunable and observable read, write, and forming pulse height and width.
    • Bypass mode - The devices are directly connected to the pads.
      • No current limiter transistors in series with the switches. So it is not recommended to perform write or forming operations.
      • Only one pixel (both its associated devices) can be bypassed at a time.
      • Pixel selection via a similar digital event-driven interface as in Neuromorphic mode.

A new neuron design

   

Use of current comparator allows precise control over the switching threshold. The current comparator is a current mode comparison circuit [by Tomazou] that does not consume any static power. 

The learning algorithm implemented on chip

  • Inspired by a biological model based on work by Walter Senn. 
  • Well-suited to train multi-layer networks using target propagation
  • Algorithm where each layer is trained as a perceptron.