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Dynap-sel – A mixed-signal multi-core spiking chip for models of cortical computation implemented in advanced ST 28nm FDSOI process.


DynapSEL is a five-core fully-asynchronous mixed-signal spiking neural network chip with on-chip learning (STDP) fabricated in 28nm FDSOI process with a silicon area of 2.8mm x 2.6mm. The chip comprises 4 TCAM cores with 1k analog leaky I&F neurons and 64k 15-bit TCAM synapses sub-divided in 4 cores, 1 learning core with 64 analog leaky I&F neurons, 8k digital 4-bit plastic synapses, and 8k 4-bit digital configurable synapses. In addition it integrated 5 LUTs with totally 8.5k x18-bit SRAMs. 3-level hierarchical routers, 2 low temperature coefficient Bias Generators supplying totally 190 branches of biases, on-chip monitors for real-time monitoring on-chip internal currents. 4 26-bit Bi-directional buffers are added in four directions for chip extensions.

Hierarchical routing scheme

dynapSEL routing

Chip information

Chip NameDynapSEL
Process ST 28nm FDSOI
Supply Voltage 0.73V - 1V
IO Number 176
Chip area 2.8mm x 2.6mm
Core Numbers 4 non-plastic cores +  1 plastic core
Neuron Type Analog AExp I&F  
Neuron Area 20um^2
Non-plastic Synapse Type TCAM based 4-bit
Non-plastic Synapse Area 7.69um^2
Plastic Synapse Type Linear 4-bit digital
Plastic Synapse Area 72.5um^2
Throughput of Router 1G Events/second
Scalability 16 x16 chips non-plastic core)  / 4 x4 chips (plastic cores)

Comparing with TrueNorth

True NorthThis work 
Technology 28nm CMOS 28 nm FDSOI
Supply Voltage 0.7V 0.73V
Neuron Type Digital Analog
Neurons per core 256 256
On-line Learning No On-line STDP
Core Area 0.094 mm^2 0.36 mm^2
Computation Time multiplexing Parallel processing
Fan In/Out 256/256 2k/8k
Synaptic Operation per Second per Watt 46 GSOPS/W 320 GSOPS/W
Energy per synaptic event 10 pJ 2.8pJ

On line STDP




On line tiny current monitors

up to 23 current monitors (current to frequency converter) are placed on chip for real-time monitoring tiny currents (pA-100nA).